Title :
Design for (physical) debug for silicon microsurgery and probing of flip-chip packaged integrated circuits
Author :
Livengood, Richard H. ; Medeiros, Donna
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
As transistor technology shrinks, well-planned structures for debug must be designed into the circuitry. Analyzing signals from the backside using pre-planned probing structures, or fixing logic or speed bugs using on-silicon microsurgery has become even more important as the photomasks and other lithographic costs climb. Quick and reliable throughput of silicon fixes is critical to the success of debug, which multi-layer tapeouts cannot provide in a timely fashion
Keywords :
chip scale packaging; design for testability; elemental semiconductors; flip-chip devices; integrated circuit testing; logic testing; silicon; IC testing; Si; Si microsurgery; critical design hooks; design for debug; fixing logic; flip-chip packaged integrated circuits; laser voltage probe; multi-layer tapeouts; probing structures; spare logic; speed bugs; Circuit analysis; Computer bugs; Costs; Logic; Microsurgery; Signal analysis; Silicon; Surgery; Throughput; Transistors;
Conference_Titel :
Test Conference, 1999. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-5753-1
DOI :
10.1109/TEST.1999.805819
