Silicon debug: scan chains alone are not enough

For today´s multi-million transistor designs, existing design verification techniques cannot guarantee that first silicon is designed error free. Therefore, techniques are necessary to efficiently debug first-silicon. In this article, we present a methodology for debugging multiple clock domain systems-on-a-chip. In addition to scan chains, a set of design-for-debug modules is designed into an IC to make it debuggable. Debugger tool software interacts with the on-chip DfD to make the debug features available from a workstation