Title :
Industrial evaluation of stress combinations for march tests applied to SRAMs
Author :
Schanstra, Ivo ; Van de Goor, Ad J.
Author_Institution :
Device Eng. Dept., Philips Semiconductors MOS4YOU, Nijmegen, Netherlands
Abstract :
This paper presents the results of ten well-known memory test algorithms and four memory test primitives applied to 3876 256 Kbit SRAM chips, using 128 different stress combinations with each test algorithm. The results show that stress combinations influence the coverage of the test algorithms for these SRAMs, and that the influence is less for these SRAMs than for DRAMs. Selecting the right stress combination allows for using a simpler algorithm. The simple memory test primitives can detect all faults given the proper stresses. Power supply voltage turns out to be a very important non-algorithmic stress
Keywords :
CMOS memory circuits; SRAM chips; fault diagnosis; integrated circuit testing; logic testing; 256 Kbit; CMOS SRAM cell; SRAM chips; addressing type; algorithm coverage; data inversion; fault detection; march tests; memory test algorithms; memory test primitives; power supply voltage stress; stress combinations; Fault detection; Manufacturing processes; Power supplies; Random access memory; SRAM chips; Semiconductor device testing; Stress; System testing; Timing; Voltage;
Conference_Titel :
Test Conference, 1999. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-5753-1
DOI :
10.1109/TEST.1999.805831
