Title :
A low area pipelined 2-D DCT architecture for JPEG encoder
Author :
Zhang, Qihui ; Meng, Nan
Author_Institution :
Sch. of Phys. & Electron., Henan Univ., Kaifeng, China
Abstract :
In this paper, a novel architecture for two-dimensional discrete cosine transform (2-D DCT) is proposed. The 2-D DCT calculation exploits the separability property and allows row-column decomposition by using 2 successive one-dimensional (1-D) transforms, whose intermediate results are transposed with a parallel transposition memory. High operating frequency can be reached and pipeline technique is adopted by additional SIPO, PISO and register banks. Moreover, the 2-D DCT architecture can be used as an inverse DCT by aiding a simple control circuitry. Compared with other implementations, our proposed architecture exhibits an operation frequency of 210 MHz and costs only 30879 equivalent gates. The proposed low area pipelined 2-D DCT architecture can be modularized and suitably reused in many image and video codec systems. The final layout of an application to our JPEG encoder for grayscale images is carried out in a 0.13 mum CMOS technology.
Keywords :
CMOS memory circuits; data compression; discrete cosine transforms; pipeline processing; video codecs; video coding; CMOS technology; JPEG encoder; discrete cosine transform; frequency 210 MHz; parallel transposition memory; pipelined 2-D DCT architecture; row-column decomposition; size 0.13 mum; video codec system; CMOS technology; Circuits; Costs; Discrete cosine transforms; Discrete transforms; Frequency; Pipelines; Registers; Two dimensional displays; Video codecs;
Conference_Titel :
Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on
Conference_Location :
Cancun
Print_ISBN :
978-1-4244-4479-3
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2009.5235989