DocumentCode :
3331282
Title :
Redundancy techniques for high-density DRAMs
Author :
Horiguchi, Masashi
Author_Institution :
Semicond. & Integrated Circuits Div., Hitachi Ltd., Tokyo, Japan
fYear :
1997
fDate :
8-10 Oct 1997
Firstpage :
22
Lastpage :
29
Abstract :
This paper describes the redundancy techniques for high-density DRAMs to solve the following two problems which arise with the increase in memory capacity: (1) the increase in memory-array division reduces the replacement flexibility between defective lines and spare lines; (2) the defects causing DC-characteristics faults, especially excessive standby current faults cannot be repaired with the conventional redundancy techniques. First, two approaches to solve the first problem are discussed: enhancing the replacement flexibility within the limits of intra-subarray replacement, and the introduction of inter-subarray replacement. Next, the recent proposals to solve the second problem are reported. The DC-characteristics faults are repaired through the modification of bitline precharge circuit or the subarray-replacement redundancy
Keywords :
DRAM chips; cellular arrays; fault diagnosis; redundancy; DC-characteristics faults; bitline precharge circuit; defective lines; high-density DRAMs; inter-subarray replacement; intra-subarray replacement; memory capacity; memory-array division; redundancy techniques; replacement flexibility; standby current faults; Circuit faults; Decoding; Degradation; Fault tolerance; Fuses; Proposals; Random access memory; Redundancy; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Innovative Systems in Silicon, 1997. Proceedings., Second Annual IEEE International Conference on
Conference_Location :
Austin, TX
ISSN :
1094-7116
Print_ISBN :
0-7803-4276-3
Type :
conf
DOI :
10.1109/ICISS.1997.630243
Filename :
630243
Link To Document :
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