Title :
HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs
Author :
Benso, Alfredo ; Cataldo, Silvia ; Chiusano, Slvia ; Prinetto, Polo ; Zorian, Yervant
Author_Institution :
Dipt. di Autom. e Inf., Politecnico di Torino, Italy
Abstract :
This paper proposes HD-BIST, a complete framework to support the definition of the scheduling strategy and mechanism of the BISTed blocks of a complex system. Three different layers are presented, to define the HD-BIST approach in terms of a set of high-level BIST scheduling primitives, a communication protocol, and a possible hardware implementation, respectively
Keywords :
automatic testing; built-in self test; embedded systems; integrated circuit testing; logic testing; microprocessor chips; BIST diagnosis; BIST scheduling; HD-BIST; SoC; application layer; communication protocol; complex system; hardware implementation; hierarchical framework; high-level BIST; Access protocols; Built-in self-test; Centralized control; Costs; Digital systems; Hardware; Logic testing; Routing; Scheduling algorithm; System testing;
Conference_Titel :
Test Conference, 1999. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-5753-1
DOI :
10.1109/TEST.1999.805837
