DocumentCode
3331370
Title
HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs
Author
Benso, Alfredo ; Cataldo, Silvia ; Chiusano, Slvia ; Prinetto, Polo ; Zorian, Yervant
Author_Institution
Dipt. di Autom. e Inf., Politecnico di Torino, Italy
fYear
1999
fDate
1999
Firstpage
1038
Lastpage
1044
Abstract
This paper proposes HD-BIST, a complete framework to support the definition of the scheduling strategy and mechanism of the BISTed blocks of a complex system. Three different layers are presented, to define the HD-BIST approach in terms of a set of high-level BIST scheduling primitives, a communication protocol, and a possible hardware implementation, respectively
Keywords
automatic testing; built-in self test; embedded systems; integrated circuit testing; logic testing; microprocessor chips; BIST diagnosis; BIST scheduling; HD-BIST; SoC; application layer; communication protocol; complex system; hardware implementation; hierarchical framework; high-level BIST; Access protocols; Built-in self-test; Centralized control; Costs; Digital systems; Hardware; Logic testing; Routing; Scheduling algorithm; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1999. Proceedings. International
Conference_Location
Atlantic City, NJ
ISSN
1089-3539
Print_ISBN
0-7803-5753-1
Type
conf
DOI
10.1109/TEST.1999.805837
Filename
805837
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