Title :
Delay fault testing of IP-based designs via symbolic path modeling
Author :
Kim, Hyungwon ; Hayes, John P.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Abstract :
Delay testing of designs that contain intellectual property (IF) cores is challenging. We propose a method that can test paths traversing both IP cores and user-defined blocks. It employs a highly efficient BDD-based path modeling method and an associated ATPG technique. Experimental results show that it robustly tests selected paths without using extra logic, and, at the same time, protects the intellectual property
Keywords :
VLSI; automatic test pattern generation; delays; fault diagnosis; industrial property; integrated circuit testing; logic testing; ATPG; IP-based design; SPMTEST; delay testing; intellectual property; symbolic path modeling; Automatic test pattern generation; Circuit faults; Circuit testing; Delay; Intellectual property; Logic circuits; Logic testing; Registers; Sociotechnical systems; System testing;
Conference_Titel :
Test Conference, 1999. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-5753-1
DOI :
10.1109/TEST.1999.805838
