DocumentCode :
3331490
Title :
How to lay out arrays spared by rows and columns
Author :
LaForge, Laurence E.
Author_Institution :
Embry-Riddle Aeronaut. Univ., USA
fYear :
1997
fDate :
8-10 Oct 1997
Firstpage :
30
Lastpage :
40
Abstract :
Perhaps the most common fault tolerant architecture configures a nominal t×at array using bt dedicated spare rows and ct dedicated spare columns. We counterexample an outstanding conjecture by constructively showing how dedicated sparing can be laid out in area proportional to the number of elements. However, we find that dedicated sparing is more costly than homogeneous extraction of a t×at array from a (1+b)t×(a+c)t array. i) In the presence of failures whose distribution is worst-case, iid, or clustered, the fault tolerance of either architecture is Θ(t-1). ii) At constant proportion of failures, the area of homogeneous arrays is Θ(exp t), while that of dedicated sparing is Ω(exp t). iii) The worst-case wirelength of either architecture is Θ(ct). iv) The best-case wirelength Θ(1) of homogeneous sparing is less than that Θ(t) of dedicated sparing. V) Probabilisticaily, homogeneous sparing has O(log t) wirelength, less than that Θ(t) of dedicated sparing. For large t, moreover, row-column sparing is more costly than local sparing
Keywords :
fault tolerant computing; reconfigurable architectures; systolic arrays; configuration architecture; dedicated sparing; fault tolerance; fault tolerant architecture; homogeneous extraction; local sparing; spare columns; spare rows; systolic arrays; worst-case wirelength; Degradation; Fault tolerance; Geometry; Switches; Systolic arrays; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Innovative Systems in Silicon, 1997. Proceedings., Second Annual IEEE International Conference on
Conference_Location :
Austin, TX
ISSN :
1094-7116
Print_ISBN :
0-7803-4276-3
Type :
conf
DOI :
10.1109/ICISS.1997.630244
Filename :
630244
Link To Document :
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