DocumentCode
3331501
Title
Design for test and time to market-friends or foes
Author
Turino, Jon
Author_Institution
SynTest Technol. Inc., USA
fYear
1999
fDate
1999
Firstpage
1098
Lastpage
1101
Abstract
This paper describes the interactions between early decisions made regarding design for testability and their impact during the product design and test development phases of a product´s life cycle on overall time to market for the product
Keywords
automatic testing; built-in self test; design for testability; integrated circuit testing; logic testing; product development; ATPG; VHDL; design for testability; product design; product development; product´s life cycle; system on chip design; test development; time to market; Built-in self-test; Circuit faults; Circuit testing; Controllability; Costs; Delay; Design for testability; Life testing; Product design; Time to market;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1999. Proceedings. International
Conference_Location
Atlantic City, NJ
ISSN
1089-3539
Print_ISBN
0-7803-5753-1
Type
conf
DOI
10.1109/TEST.1999.805844
Filename
805844
Link To Document