Low-power memory addressing scheme for fast fourier transform processors

In this paper, a new memory addressing architecture is proposed for low-power radix-2 FFT implementations. Two optimization schemes are presented for dynamic power reduction. First, a multi-bank memory structure is introduced. Second, twiddle factor access times are significantly reduced with a new addressing sequence. For performance evaluation, FFT kernels with transform sizes ranging from 16 to 512 are implemented in CMOS 0.18 mu technology. The synthesis results and architectural analysis indicate significant switching power reduction with no performance penalty. Power reduction factor grows with the transform size, making this architecture ideal for applications requiring long FFT operations.