Title :
Clock cycle estimations for future microprocessor generations
Author_Institution :
SEMATECH, Austin, TX
Abstract :
In the past 50 years, the semiconductor industry has experienced unprecedented growth. Identifying pivotal factors and technology trends in future generations will be key to understanding how we can maintain the historical growth and improve customer value. Processor performance will be one of the essential factors in this quest. This paper presents a high-level model of microprocessor clock-cycle performance. The model considers the impact of interconnect technology, device and circuit technology, along with architectural and physical design factors, to estimate clock speeds of future microprocessors
Keywords :
clocks; integrated circuit design; integrated circuit modelling; integrated circuit technology; microprocessor chips; technological forecasting; architectural design factors; circuit technology; clock cycle estimations; customer value; future microprocessor generations; high-level model; interconnect technology; physical design factors; semiconductor industry; technology trends; Clocks; Computer aided instruction; Computer architecture; Delay; Electronic mail; Electronics industry; Frequency estimation; Integrated circuit interconnections; Microprocessors; Pipeline processing;
Conference_Titel :
Innovative Systems in Silicon, 1997. Proceedings., Second Annual IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-4276-3
DOI :
10.1109/ICISS.1997.630247
