Low-complexity implementation of state-space structures in linear DSP synthesis

In recent times, we have seen that shift-and-add operations have replaced multiplication for efficient hardware implementation to achieve reduction in hardware and power. Previously, researchers have proposed methods combining architectural transformations and shift-and-add decompositions for hardware optimizations. In this paper, a highly efficient common subexpression elimination (CSE) algorithm based on the binary representation of the system matrices to optimize the hardware requirements in linear Digital Signal Processing (DSP) synthesis is proposed. The algorithm chooses the maximum number of frequently occurring subexpressions to eliminate redundant computations and hence reduces the number of adders required to implement the multiplications in the state space model. Design examples of systems show that the proposed method offers a hardware reduction of around 22% over the previously best known method.