Performance evaluation of multi-operand fast decimal adders

A renewed interest in decimal arithmetic has introduced several new designs for multi-operand decimal addition. For performance evaluation, this work implements, synthesizes, and compares four unsigned and four signed-digit multi-operand decimal adders on 0.18 mum CMOS VLSI technology. Furthermore, a new architecture for signed-digit decimal adders with fast implementation is proposed. Synthesis results for 2, 4, 8, and 16 operands and 8 decimal digits provide useful statistics in determining each adder´s performance and scalability. The results unambiguously highlight the advantages and disadvantages of each approach.