DocumentCode
3332407
Title
A new bit-serial architecture of rank-order filter
Author
Yamamoto, Takuya ; Moshnyaga, Vasily G.
Author_Institution
Dept. Electron. Eng. & Comput. Sci., Fukuoka Univ., Fukuoka, Japan
fYear
2009
fDate
2-5 Aug. 2009
Firstpage
511
Lastpage
514
Abstract
This paper presents a new architecture of rank-order median filter. The architecture processes all window samples in parallel in the bit-serial manner. Unlike related architectures, it neither sorts/swaps nor modifies the window samples and requires less hardware resources. To process k samples, each of N-bits in size, the architecture uses N shift registers of k bits each and a simple logic. It produces the result in N+1 clock cycles independently to the window size.
Keywords
median filters; parallel architectures; N+1 clock cycles; bit-serial architecture; hardware resources; rank-order median filter; Clocks; Computer architecture; Computer science; Filtering; Filters; Hardware; Polarization; Shift registers; Signal processing; Sorting;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on
Conference_Location
Cancun
ISSN
1548-3746
Print_ISBN
978-1-4244-4479-3
Electronic_ISBN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2009.5236042
Filename
5236042
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