Manufacturable low-power latches for standard tied-double-gate FinFET technologies

A low-power manufacturable multi-threshold voltage (multi-V_th) brute force latch based on gate-drain/source overlap engineering in standard tied-gate FinFET technologies is proposed in this paper. Various tied-gate FinFET latch design options are evaluated for active mode power consumption, propagation delay, setup time, leakage power consumption, and static noise margin. With the proposed latch based on gate overlap engineering, the total active mode power consumption, the clock power, and the average leakage power are reduced by up to 62%, 21%, and 45%, respectively, while maintaining similar speed and data stability as compared to the standard circuits in a 32 nm symmetric tied-double-gate FinFET technology.