Optimization of oversampling Data Recovery

The paper deals with the design and optimization of blind oversampling clock and data recovery (CDR) based on FPGA prototyping. The main advantage of the oversampling CDR is the fully digital architecture, which enables the FPGA-based testing and its subsequent integration into any ASIC technology. The oversampling CDR is a promising block for free space optical (FSO) applications because of its extremely short reacquisition time, which is the key feature for efficient communication over the frequently fading channel. An efficient statistical simulation model for the CDR optimization is presented. Our effort in optimization was focused mainly on the simplification of the decision algorithm while maintaining acceptable jitter tolerance. The suggested method was verified on the Xilinx FPGA platform.