Pulse width variation tolerant clock tree using unbalanced cells for low power design

Global and environmental variations including process (P), voltage (V) and temperature (T) constitute the biggest factor among all variations for any ASIC design. The age-old approach of using corners and margins to quantify the impact of variations is still applicable but the increasing margins limit the scaling of max achievable design frequency with technology, especially because of minimum pulse width violation. ASIC designs in current technology are working at these max clock frequencies. Moreover, as the importance of global N-to-P mismatch increases with technology, it increases the sensitivity of clock tree pulse-width to variations. Thus, to continue to scale the clock frequency in the future, we need to make margins and corners that are application specific. In this work, we have estimated the impact of PVT variations on the standard cells in a clock library using industrial models and SPICE simulations. We found that unbalancing the first stage with respect to the pulse edges in a cell reduced the variations by a factor of three without affecting the output behavior. We also found cells with opposite pulse-width variation characteristics enabling their combination in a path to minimize the overall variations.