A Hybrid Scheduling Technique for Hierarchical Logic Simulators or "Close Encounters of the Simulated Kind"

Advancing circuit complexity in LSI technology has brought about an ever growing need for more powerful Computer Aided Design tools. Verification of an IC design through simulation is mandatory to avoid costly mask iterations and delays in product introduction due to design errors. A gate level simulation is one method for reducing errors in a chip design. However, gate level simulations of large designs are extremely expensive. A high level "black box" or functional simulation gains in efficiency, yet loses accuracy. It is possible to minimize the individual disadvantages of these two approaches with a hierarchical simulator that permits a mixture of the two levels. Further improvement can be realized by incorporating a dual mode (fixed event list/event-driven) scheduler within this hierarchical simulation environment to control more efficiently the model evaluation sequence. This paper describes such a scheduler, and the user interfaces for it.