• DocumentCode
    3332977
  • Title

    Double-sampled ΔΣ modulator with relaxed feedback timing

  • Author

    Shen, Weilun ; Temes, Gabor C.

  • Author_Institution
    Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA
  • fYear
    2009
  • fDate
    2-5 Aug. 2009
  • Firstpage
    393
  • Lastpage
    396
  • Abstract
    A new double-sampled delta-sigma modulator topology is proposed to relax the critical timing constraints in the modulator feedback path, thus the speed requirement of the quantizer and DEM logic can be greatly reduced. To verify the proposed modulator topology, a second-order double-sampled delta-sigma modulator was designed and simulated.
  • Keywords
    delta-sigma modulation; modulators; network topology; quantisation (signal); DEM logic; critical timing constraints; delta-sigma modulator topology; double-sampled DeltaSigma modulator; dynamic element matching algorithms; quantizer; relaxed feedback timing; Bandwidth; CMOS technology; Clocks; Computed tomography; Delta modulation; Feedback; Frequency; Sampling methods; Timing; Topology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on
  • Conference_Location
    Cancun
  • ISSN
    1548-3746
  • Print_ISBN
    978-1-4244-4479-3
  • Electronic_ISBN
    1548-3746
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2009.5236073
  • Filename
    5236073
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3332977