Track-and-hold and comparator for a 12.5GS/s, 8bit ADC

This paper discusses the design and characterization of a track-and-hold amplifier (THA) and a comparator which are the essential building blocks of an 8 bit, 12.5 GS/s folding-interpolating analog to digital converter (ADC) with a 3 GHz bandwidth. The circuits are implemented in a 0.25 mum, 190 GHz SiGe BiCMOS process. The THA occupies an area of 0.5 mm². It features a SNDR of 47 dB or 7.5 bits ENOB for a 3 GHz bandwidth, a hold time of 21 ps with a droop rate of 11 mV/80 ps and a power dissipation of 230 mW from a 3.3 V supply. The comparator occupies an area of 0.38 mm² and exhibits an input sensitivity of plusmn2 mV, an input offset voltage of 1.5 mV, latch and recovery times of 19 and 21 ps respectively and a power dissipation of 150 mW from a 3.3 V supply.