DocumentCode :
3333233
Title :
Design and Verification of Large-Scale Computers by Using DDL
Author :
Kawato, Nobuaki ; Saito, Takao ; Maruyama, Fumihiro ; Uehara, Takao
Author_Institution :
FUJITSU Laboratories Ltd., Kawasaki, Kanagawa, Japan
fYear :
1979
fDate :
25-27 June 1979
Firstpage :
360
Lastpage :
366
Abstract :
This paper describes the total support system for DDL which has been approved by design engineers at Fujitsu. A simulator is used not only at register transfer level but also with gate level description. The translator generates gate level designs which are then optimized by designers. The verifier has powerful functions to detect conflicts in specification and its implementation.
Keywords :
Automatic control; Computational modeling; Computer aided instruction; Design optimization; Large scale integration; Large-scale systems; Logic design; Registers; Software systems; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1979. 16th Conference on
Type :
conf
DOI :
10.1109/DAC.1979.1600137
Filename :
1600137
Link To Document :
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