• DocumentCode
    3333252
  • Title

    Logic Verification System for Very Large Computers Using LSI´s

  • Author

    Ohno, Yasuhiro ; Miyoshi, Masayuki ; Sato, Katsuya

  • Author_Institution
    Kanagawa Works, Hitachi, Ltd.,Kanagawa, Japan
  • fYear
    1979
  • fDate
    25-27 June 1979
  • Firstpage
    367
  • Lastpage
    374
  • Abstract
    To aid design verification of very large computers using many LSI´s, software tools including a logic simulator with capability of 750,000 gates have been developed.
  • Keywords
    Circuit simulation; Circuit testing; Computer errors; Delay; Large scale integration; Logic circuits; Logic design; Logic testing; Optical design; Process design;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1979. 16th Conference on
  • Type

    conf

  • DOI
    10.1109/DAC.1979.1600138
  • Filename
    1600138
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3333252