Title :
Tutorial: digital neurocomputing for signal/image processing
Author_Institution :
Princeton Univ., NJ, USA
fDate :
30 Sep-1 Oct 1991
Abstract :
The requirements on both the computations and storage for neural networks are extremely demanding. Neural information processing would be practical only when efficient and high-speed computing hardware can be made available. The author reviews several approaches to architecture and implementation of neural networks for signal and image processing. The author discusses direct design of dedicated neural networks implemented by a variety of hardware technologies (e.g. CMOS, CCD), and introduces an indirect design approach based on matrix-based mapping methodology for systolic/wavefront array processor. The array processors mapping technique presented should be applicable to both programmable neurocomputer and dedicated digital or analog neural processing circuits. Several key general-purpose and system-oriented designs are surveyed. Key design examples of existing parallel processing neurocomputers are also discussed
Keywords :
digital signal processing chips; image processing; neural chips; signal processing; systolic arrays; analog neural processing circuits; dedicated digital processing circuit; dedicated neural networks; digital neurocomputing; image processing; matrix-based mapping methodology; neural networks; signal processing; systolic array processor; wavefront array processor; CMOS process; CMOS technology; Computer architecture; Computer networks; Image processing; Information processing; Neural network hardware; Neural networks; Signal processing; Tutorial;
Conference_Titel :
Neural Networks for Signal Processing [1991]., Proceedings of the 1991 IEEE Workshop
Conference_Location :
Princeton, NJ
Print_ISBN :
0-7803-0118-8
DOI :
10.1109/NNSP.1991.239479
