A low-latency serial architecture for the 1-D discrete wavelet transform

Author

Breveglieri, Luca ; Piuri, Vincenzo ; Rona, Marco ; Swartzlander, Earl E., Jr.

Author_Institution

Dept. of Electron. & Inf., Politecnico di Milano, Italy

fYear

1997

fDate

8-10 Oct 1997

Firstpage

300

Lastpage

309

Abstract

The 1-Dimensional Discrete Wavelet Transform is a powerful DSP technique for several application areas. Dedicated VLSI processors are often required by real-time applications due to the high amount of arithmetic operations; the circuit complexity is usually a relevant constraint for several low-cost applications as well as for complex systems having strong dimensional limits on the implementation (e.g., in aerospace applications). This paper presents the architectural design of a low-latency bit-serial 1-Dimensional Wavelet Transform Processor

Keywords

VLSI; digital signal processing chips; transforms; wavelet transforms; DSP; VLSI processor; aerospace application; bit-serial architecture; circuit design; latency; one-dimensional discrete wavelet transform; real-time arithmetic operations; Application software; Complexity theory; Digital signal processing; Discrete wavelet transforms; Low pass filters; Signal processing; Signal processing algorithms; Very large scale integration; Video compression; Wavelet transforms;

fLanguage

English

Publisher

ieee

Conference_Titel

Innovative Systems in Silicon, 1997. Proceedings., Second Annual IEEE International Conference on

Conference_Location

Austin, TX

ISSN

1094-7116

Print_ISBN

0-7803-4276-3

Type

conf

DOI

10.1109/ICISS.1997.630273

Filename

630273