Reliability modeling of transistor gates at the nanoscale

The efficacy of any product and process, including safety and functionality during the system lifecycle is defined by its reliability. Already essential for macro- and microsystems, reliability is even more critical in the nano realm due to expected higher functionality and complexity of products. Although reliability estimates are indispensable to validate visionary research and development of scalable, produceable and useable nanodevices, very little work has been reported on critical reliability issues. It is well known from macro systems that neglecting reliability in the early conception and design stages results in high costs later on in the product lifecycle. Such neglect could render supposedly revolutionary ideas totally unusable. Reliability theory and related physics of failure concepts for traditional macro systems/products have not transferred readily to the nano scale. Our work is an attempt to examine the feasibility of porting what works in the macro realm to the nano realm and specifically the reliability of high-k dielectric material. A degradation model is proposed and a methodology of statistical reliability analysis presented. In addition, several sources of dielectric substrate degradation data are also suggested.