Title :
Design and implementation of charge-pump phase-locked loop
Author :
Min-Chin Lee ; Ming-Chia Hsieh ; Ya-Ciou Lin
Author_Institution :
Oriental Inst. of Technol., Taipei, Taiwan
Abstract :
A phase-locked loop with charge pump approach is design and implemented using the TSMC 0.35 μm CMOS 2P4M process. The output frequency generated from the phase-frequency detector is compared with the reference frequency. This output frequency is then converted into current through the charge-pump. This current is further converted into voltage through loop filter to control oscillator. Because the output frequency is too high it is reduced by the frequency divider for comparison. According to simulated and measured results, the CPPLL centered at 500 MHz output frequency, chip size is 1.023×1.011mm2, power dissipation about 10 mW, and the jitter is 80ps.
Keywords :
CMOS analogue integrated circuits; charge pump circuits; frequency dividers; phase detectors; phase locked loops; CPPLL; TSMC CMOS 2P4M process; charge-pump phase-locked loop; frequency 500 MHz; frequency divider; loop filter; oscillator; phase-frequency detector; reference frequency; size 0.35 mum; Charge pumps; Frequency conversion; Frequency measurement; Low pass filters; Phase locked loops; Semiconductor device measurement; Voltage-controlled oscillators; CPPLL; Charge Pump; Frequency Divider; Voltage-Control Oscillator;
Conference_Titel :
Electromagnetics, Applications and Student Innovation (iWEM), 2011 IEEE International Workshop on
Conference_Location :
Taipei
Print_ISBN :
978-1-61284-462-6
Electronic_ISBN :
978-1-61284-461-9
DOI :
10.1109/iWEM.2011.6021491
