High aspect ratio through-wafer interconnections for 3D-microsystems

Author

Wang, Lingfeng ; Nichelatti, A. ; Schellevis, H. ; de Boer, C. ; Visser, C. ; Nguyen, T.N. ; Sarro, P.M.

Author_Institution

DIMES, Delft Univ. of Technol., Netherlands

fYear

2003

fDate

19-23 Jan. 2003

Firstpage

634

Lastpage

637

Abstract

Closely spaced, through-wafer interconnects are of large interest in RF MEMS and MEMS packaging. In this paper, a suitable technique to realize large arrays of small size through-wafer holes is presented. This approach is based on macroporous silicon formation in combination with wafer thinning. Very high aspect ratio (≥ 100) structures are realized. The wafers containing the large arrays of 2-3μm wide holes are thinned down to 200-150μm by lapping and polishing. Copper electroplating is finally employed to realize arrays of high aspect ratio Cu plugs.

Keywords

copper; electroplated coatings; integrated circuit interconnections; integrated circuit packaging; micromechanical devices; polishing; 2 to 3 micron; 200 to 150 micron; 3D-microsystems; Cu; MEMS packaging; RF MEMS; copper electroplating; high aspect ratio through-wafer interconnections; Anisotropic magnetoresistance; Copper; Etching; Lapping; Micromechanical devices; Packaging; Plugs; Radiofrequency microelectromechanical systems; Silicon; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Micro Electro Mechanical Systems, 2003. MEMS-03 Kyoto. IEEE The Sixteenth Annual International Conference on

ISSN

1084-6999

Print_ISBN

0-7803-7744-3

Type

conf

DOI

10.1109/MEMSYS.2003.1189829

Filename

1189829