DocumentCode :
3334226
Title :
Design space exploration of present implementations for FPGAS
Author :
Sbeiti, Mohamad ; Silbermann, Michael ; Poschmann, Axel ; Paar, Christof
Author_Institution :
Embedded Security Group, Horst Gortz Inst. for IT Security, Bochum
fYear :
2009
fDate :
1-3 April 2009
Firstpage :
141
Lastpage :
145
Abstract :
In this paper we investigate the performance of the block cipher PRESENT on FPGAs. We provide implementation results of an efficiency (i.e. throughput per slice) optimized design and compare them with other block ciphers. Though PRESENT was originally designed with a minimal hardware footprint in mind, our results also highlight that PRESENT is well suited for high-speed and high-throughput applications. Especially its hardware efficiency, i.e. the throughput per slice, is noteworthy.
Keywords :
cryptography; field programmable gate arrays; FPGA; PRESENT block cipher; design space exploration; hardware efficiency; high-speed application; high-throughput application; Application specific integrated circuits; Computer architecture; Cryptography; Design optimization; Field programmable gate arrays; Hardware; Security; Space exploration; System-on-a-chip; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Programmable Logic, 2009. SPL. 5th Southern Conference on
Conference_Location :
Sao Carlos
Print_ISBN :
978-1-4244-3847-1
Type :
conf
DOI :
10.1109/SPL.2009.4914893
Filename :
4914893
Link To Document :
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