Decimal addition in FPGA

This paper presents a study of the classical BCD adders from which a carry-chain type adder is redesigned to fit within the Xilinx FPGAs. Some new concepts are presented to compute the P and G functions for carry-chain optimization purposes. Several alternative designs are then presented with the corresponding time performances and area consumption figures. In order to compare the results, the straight implementation of a decimal ripple-carry adder and the FPGA optimized base 2 adder for the same range are implemented. Results for big operands show that the decimal adder works faster than an equivalent binary implementation and furthermore the coding / decoding processes are no more needed.