Decimal addition in FPGA

Author

Bioul, G. ; Vazquez, M. ; Deschamps, J.P. ; Sutter, G.

Author_Institution

FASTA Univ., Mar del Plata

fYear

2009

fDate

1-3 April 2009

Firstpage

101

Lastpage

108

Abstract

This paper presents a study of the classical BCD adders from which a carry-chain type adder is redesigned to fit within the Xilinx FPGAs. Some new concepts are presented to compute the P and G functions for carry-chain optimization purposes. Several alternative designs are then presented with the corresponding time performances and area consumption figures. In order to compare the results, the straight implementation of a decimal ripple-carry adder and the FPGA optimized base 2 adder for the same range are implemented. Results for big operands show that the decimal adder works faster than an equivalent binary implementation and furthermore the coding / decoding processes are no more needed.

Keywords

adders; binary codes; carry logic; field programmable gate arrays; BCD adder; FPGA optimized base 2 adder; G functions; P functions; Xilinx FPGA; area consumption; binary coded decimal; carry-chain optimization; carry-chain type adder; decimal addition; decimal ripple-carry adder; time performance; Adders; Application software; Data processing; Decoding; Digital arithmetic; Field programmable gate arrays; Hardware; Internet; Software libraries; Software performance;

fLanguage

English

Publisher

ieee

Conference_Titel

Programmable Logic, 2009. SPL. 5th Southern Conference on

Conference_Location

Sao Carlos

Print_ISBN

978-1-4244-3847-1

Type

conf

DOI

10.1109/SPL.2009.4914894

Filename

4914894