• DocumentCode
    3334379
  • Title

    Chipcflow- A dynamic dataflowmachine using dynamic reconfigurable hardware

  • Author

    Silva, Jorge L. ; Lopes, Joelmir J. ; Roda, Valentin O. ; Costa, Kelton P.

  • Author_Institution
    Dept. of Comput. Syst., Univ. of Sao Paulo, Sao Carlos
  • fYear
    2009
  • fDate
    1-3 April 2009
  • Firstpage
    213
  • Lastpage
    216
  • Abstract
    In order to convert High Level Language (HLL) into hardware, a Control Dataflow Graph (CDFG) is a fundamental element to be used. Otherwise, Dataflow Architecture, can be obtained directly from the CDFG. In the 1970s and late 1980s, the Dataflow Model was the focus of attention that provided parallelism in a natural form. In particular, dynamic dataflow architecture can be generated to produce a high level of parallelism. In this paper, the ChipCflow project is described as a system to convert HLL into a dynamic dataflow graph to be executed in a dynamic reconfigurable hardware, exploring the dynamic reconfiguration. The ChipCflow consists of various parts: the compiler to convert the C program into a dataflow graph; the operators and its instances; the tagged-token; and the matching data. Some results are presented in order to show a proof of concept for the project.
  • Keywords
    data flow graphs; parallel languages; C program; ChipCflow; compiler; control dataflow graph; dataflow architecture; dynamic dataflow machine; dynamic reconfigurable hardware; dynamic reconfiguration; high level language; operators; tagged-token; Computer architecture; Control systems; Field programmable gate arrays; Hardware; High level languages; Microelectronics; Parallel processing; Program processors; Protocols; Reconfigurable architectures;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Programmable Logic, 2009. SPL. 5th Southern Conference on
  • Conference_Location
    Sao Carlos
  • Print_ISBN
    978-1-4244-3847-1
  • Type

    conf

  • DOI
    10.1109/SPL.2009.4914900
  • Filename
    4914900