DocumentCode
3334483
Title
FuSE - a hardware accelerated HDL fault injection tool
Author
Jeitler, Marcus ; Delvai, Martin ; Reichör, Stefan
Author_Institution
Vienna Univ. of Technol., Vienna
fYear
2009
fDate
1-3 April 2009
Firstpage
89
Lastpage
94
Abstract
The ongoing miniaturization of digital circuits makes them more and more susceptible to faults which also complicates the design of fault tolerant systems. In this context fault injection plays an important role in the process of fault tolerance validation. As a result many fault injection tools have emerged during the last decade. However these tools only operate on specific domains and can therefore be referred to as hardware- or software-, simulation- or emulation based techniques. In this paper we present FuSE, a single fault injection tool which covers multiple domains as well as different fault injection purposes. FuSE has been designed for usage with the SEmulatorreg-an FPGA-based hardware accelerator. The created tool set has been fully automated for the fault injection process and only requires a VHDL description and a test bench of the circuit under test. FuSE can then perform fault injection experiments with a diagnostic resolution that is known from simulation-based approaches, but at a speed that even handles long running experiments with ease.
Keywords
fault tolerance; field programmable gate arrays; hardware description languages; logic design; FPGA-based hardware accelerator; FuSE; VHDL; digital circuit; fault tolerance validation; hardware accelerated HDL fault injection tool; Acceleration; Automatic testing; Circuit faults; Circuit testing; Digital circuits; Emulation; Fault tolerance; Fault tolerant systems; Fuses; Hardware design languages;
fLanguage
English
Publisher
ieee
Conference_Titel
Programmable Logic, 2009. SPL. 5th Southern Conference on
Conference_Location
Sao Carlos
Print_ISBN
978-1-4244-3847-1
Type
conf
DOI
10.1109/SPL.2009.4914906
Filename
4914906
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