DocumentCode
3334624
Title
Hardware accelerated aerial image simulation by FPGA
Author
Jamleh, Hani ; Chen, Charlie Chung-Ping
Author_Institution
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
fYear
2009
fDate
1-3 April 2009
Firstpage
39
Lastpage
44
Abstract
This paper describes a hardware implementation of aerial image simulation in lithography using FPGA. However, such simulators are presently performed using mainly software-based techniques on dedicated computers. The Hopkins partially coherent imaging equation is decomposed numerically by using singular value decomposition (SVD). The data input is a function which is consisting of rectangles as Manhattan geometry mask. For the convolution of mask functions with arbitrary kernels, a table lookup technique is used. For each single point intensity computation, it needs computation in the number of rectangles within a bounded window and the approximation order of the optical system adopted. This computation is done by FPGA on the order of O(R) instead of O(AmiddotR) which is the case in temporal machines. It is clearly shown how FPGA can be utilized efficiently to reduce the cost of computation.
Keywords
field programmable gate arrays; image processing; lithography; singular value decomposition; table lookup; FPGA; Hopkins partially coherent imaging equation; Manhattan geometry mask; hardware accelerated aerial image simulation; lithography; mask function convolution; singular value decomposition; table lookup; Acceleration; Computational modeling; Computer simulation; Equations; Field programmable gate arrays; Hardware; Lithography; Optical computing; Optical imaging; Singular value decomposition;
fLanguage
English
Publisher
ieee
Conference_Titel
Programmable Logic, 2009. SPL. 5th Southern Conference on
Conference_Location
Sao Carlos
Print_ISBN
978-1-4244-3847-1
Type
conf
DOI
10.1109/SPL.2009.4914916
Filename
4914916
Link To Document