Title :
SEE and TID Results for a RadHard-by-Design 16Mbit SRAM with Embedded EDAC
Author :
Hafer, C. ; Mabra, J. ; Slocum, D. ; Farris, T. ; Jordan, A.
Author_Institution :
Aeroflex Colorado Springs
Abstract :
Radhard-by-design has been advanced by embedding EDAC into a 16Mbit SRAM to harden the SRAM against single event upset. Conventional radhard-by-design techniques are used for the non-memory circuitry. The estimated uncorrectable double bit error rate is 2.9 times 10-16 errors/bit-day assuming a geosynchronous orbit, the Adam´s 90% worst case environment and a nominal 312 kHz scrub frequency. The device is SEL immune to a LET of 105 MeV-cm2/mg and TID hard to greater than 100 krad(Si)
Keywords :
SRAM chips; error correction; error detection; error statistics; radiation hardening (electronics); 16 Mbit; 312 kHz; SRAM; bit error rate; embedded EDAC; geosynchronous orbit; nonmemory circuitry; radhard-by-design techniques; single event upset; Bit error rate; Circuits; Error correction; Error correction codes; Event detection; Frequency estimation; Minimally invasive surgery; Random access memory; Single event upset; Springs; EDAC; RadHard-by-Design; Radiation effects; SRAM;
Conference_Titel :
Radiation Effects Data Workshop, 2006 IEEE
Conference_Location :
Ponte Vedra, FL
Print_ISBN :
1-4244-0638-2
DOI :
10.1109/REDW.2006.295481
