Systolic array implementations for real time enhancement of remote sensing imaging

In this paper, we propose a hardware/software (HW/SW) co-design approach for near real time implementation of high-resolution reconstruction of remote sensing (RS) imagery using systolic arrays as coprocessors. The proposed design is based on a field programmable gate array (FPGA) and implements the image enhancement/reconstruction tasks in an efficient concurrent processing architecture with systolic arrays that meets the (near) real time imaging systems requirements in spite of conventional computations. The software design is aimed at the algorithmic-level decrease of the computational load of the large-scale SAR image enhancement tasks. The innovative algorithmic idea is based on the concept of descriptive regularization (DR) approach. Finally, we report and discuss the results of the hardware/software co-design implementation in a Xilinx Virtex-4 XC4VSX35-10ff668 for reconstruction of large scale real world RS images of 512 times 512 pixel format.