A hierarchical multi-level test generation system

Author

Lioy, A. ; Poncino, M.

Author_Institution

Politecnico di Torino, Italy

fYear

1991

fDate

1-2 Mar 1991

Firstpage

54

Lastpage

59

Abstract

The authors describe a multi-level ATPG system which handles circuits consisting of `switch´ transistors, Boolean gates, and open-output gates (i.e., tristate, open-collector, open-emitter). Both combinational and synchronous sequential circuits are supported, with provision for full-scan, partial-scan, and non-scan design. The most remarkable features of the system are an unified approach to test generation (suitable to compiled-code implementation) and automatic extraction of hierarchy

Keywords

automatic testing; combinatorial circuits; integrated circuit testing; logic testing; sequential circuits; Boolean gates; automatic extraction; combinational circuits; compiled-code implementation; full-scan; hierarchical multilevel system; multi-level ATPG system; multi-level test generation system; nonscan design; open-collector; open-emitter; open-output gates; partial-scan; synchronous sequential circuits; tristate; Automatic test pattern generation; Automatic testing; Bidirectional control; Circuit faults; Circuit testing; Logic devices; Sequential circuits; Switches; Switching circuits; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1991. Proceedings., First Great Lakes Symposium on

Conference_Location

Kalamazoo, MI

Print_ISBN

0-8186-2170-2

Type

conf

DOI

10.1109/GLSV.1991.143942

Filename

143942