• DocumentCode
    3334743
  • Title

    Digital circuit evolution for scalability

  • Author

    She, Xiaoxuan

  • Author_Institution
    State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai
  • fYear
    2009
  • fDate
    1-3 April 2009
  • Firstpage
    183
  • Lastpage
    188
  • Abstract
    Evolvable hardware (EHW) refers to self-reconfiguration hardware design, where the configuration is under the control of an evolution algorithm. One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines evolvable hardware based on a 2-LUT (2-input lookup table) array, which allows the evolution of large circuits via decomposition. The proposed EHW has been tested with multipliers and logic circuits taken from the Microelectronics Centre of North Carolina (MCNC) benchmark library. The experimental results demonstrate that the proposed scheme improves the evolution of logic circuits in terms of the number of generations, area and delay, reduces computational time and enables the evolution of large circuits.
  • Keywords
    evolutionary computation; logic circuits; logic design; digital circuit evolution; evolvable hardware; logic circuit; multiplier; self-reconfiguration hardware design; Algorithm design and analysis; Benchmark testing; Circuit testing; Digital circuits; Hardware; Logic circuits; Logic testing; Microelectronics; Scalability; Table lookup;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Programmable Logic, 2009. SPL. 5th Southern Conference on
  • Conference_Location
    Sao Carlos
  • Print_ISBN
    978-1-4244-3847-1
  • Type

    conf

  • DOI
    10.1109/SPL.2009.4914923
  • Filename
    4914923