DocumentCode :
3335019
Title :
A massively parallel and versatile architecture for computer vision
Author :
Deb, Alak ; Ling, Nam
Author_Institution :
Chips Technol., San Jose, CA, USA
fYear :
1991
fDate :
1-2 Mar 1991
Firstpage :
74
Lastpage :
79
Abstract :
A massively parallel architecture for vision that can be efficiently implemented as a dense and regular VLSI circuit is proposed. It consists of locally connected array of simple processors possessing certain capabilities, making it possible to form a complete vision system for binary images, that can operate in real time. For low level processing both a systolic implementation on a 2D array, as well as a non-systolic `retinotopic´ processing is possible. For the intermediate level, support for pyramidal hierarchy on the array is provided. To facilitate high level vision processing on the same architecture both AI, as well as the binary neural network approaches are applied
Keywords :
VLSI; artificial intelligence; computer vision; computerised picture processing; neural nets; parallel architectures; real-time systems; systolic arrays; 2D array; AI; VLSI circuit; binary images; binary neural network; computer vision; locally connected array; machine vision; massively parallel architecture; nonsystolic retinotopic processing; pyramidal hierarchy; real time; robot vision; systolic implementation; Artificial intelligence; Circuits; Computer architecture; Computer vision; Intelligent sensors; Laser radar; Machine vision; Neural networks; Pixel; Real time systems;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 1991. Proceedings., First Great Lakes Symposium on
Conference_Location :
Kalamazoo, MI
Print_ISBN :
0-8186-2170-2
Type :
conf
DOI :
10.1109/GLSV.1991.143945
Filename :
143945
Link To Document :
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