Title :
Transition count testing of CMOS combinational circuits
Author :
Manjunath, K.S. ; Radharkrishnan, D.
Author_Institution :
Idaho Univ., Moscow, ID, USA
Abstract :
An optimal, robust transition count test generation for testing stuck-open faults in CMOS combinational circuits is presented in this paper. Procedures to optimize conventional stuck-open fault test sets have been developed. The use of fault folding graphs as a tool, to generate optimal test sequences, has been illustrated. Both non-reconvergent and reconvergent, irredundant, circuits are treated,
Keywords :
CMOS integrated circuits; combinatorial circuits; graph theory; integrated circuit testing; logic testing; CMOS combinational circuits; fault folding graphs; nonreconvergent fanout circuits; reconvergent fanout circuits; stuck-open faults; transition count test generation; CMOS logic circuits; Circuit faults; Circuit testing; Combinational circuits; Logic testing; NASA; Robustness; Semiconductor device modeling; System testing; Very large scale integration;
Conference_Titel :
VLSI, 1991. Proceedings., First Great Lakes Symposium on
Conference_Location :
Kalamazoo, MI
Print_ISBN :
0-8186-2170-2
DOI :
10.1109/GLSV.1991.143951
