Title :
A parallel SRT divider for systolic linear system solvers
Author :
Nienhaus, Harry A. ; Monemi, Cameron
Author_Institution :
Dept. of Electr. Eng., South Florida Univ., Tampa, FL, USA
Abstract :
The design and simulation results for a CMOS parallel SRT divider which produces a 16-bit quotient from a 16-bit floating-point dividend and a 16-bit floating-point divisor are described. The divider used mixed-radix signed-digit numbers for the quotient before decoding. A behavioral simulator which implements the detailed algorithms, has been written for the divider in C. Simulation results have been compared to computer division for 1000 random test vectors. Timing simulations using the simulator FACTS give worst-case propagation delays of 326.5 ns using 3-μm CMOS parametric data
Keywords :
CMOS integrated circuits; cellular arrays; digital arithmetic; digital simulation; parallel architectures; 16 bit; CMOS parallel SRT divider; CMOS parametric data; behavioral simulator; computer division; floating-point dividend; floating-point divisor; mixed-radix signed-digit numbers; quotient; random test vectors; simulation results; simulator FACTS; systolic linear system solvers; timing simulations; worst-case propagation delays; Adders; Bars; CMOS process; Circuits; Decoding; Hardware; Linear systems; Process design; Propagation delay; Systolic arrays;
Conference_Titel :
Southeastcon '89. Proceedings. Energy and Information Technologies in the Southeast., IEEE
Conference_Location :
Columbia, SC
DOI :
10.1109/SECON.1989.132644
