Title :
Fault simulation of I/sub DDQ/ tests for bridging faults in sequential circuits
Author :
Thadikaran, P. ; Chakravarty, S. ; Patel, J.
Author_Institution :
Dept. of Comput. Sci., State Univ. of New York, Buffalo, NY, USA
Abstract :
The notion of indistinguishable pairs is introduced. Two methods to compute such pairs-an explicit scheme and an implicit scheme-are presented. The resulting fault simulation algorithms, list-based scheme and tree-based scheme are compared using a variety of faultlists and test sets. The performance of the tree-based scheme is found to be superior to the list-based scheme. Applications where the list-based scheme perform better are discussed.<>
Keywords :
circuit analysis computing; digital simulation; fault diagnosis; fault trees; list processing; logic testing; sequential circuits; I/sub DDQ/ tests; bridging faults; explicit scheme; fault simulation; fault simulation algorithms; faultlists; implicit scheme; indistinguishable pairs; list-based scheme; sequential circuits; test sets; tree-based scheme; CMOS logic circuits; CMOS technology; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Current measurement; Logic circuits; Sequential analysis; Sequential circuits;
Conference_Titel :
Fault-Tolerant Computing, 1995. FTCS-25. Digest of Papers., Twenty-Fifth International Symposium on
Conference_Location :
Pasadena, CA, USA
Print_ISBN :
0-8186-7079-7
DOI :
10.1109/FTCS.1995.466965
