VLSI design of a high-throughput discrete cosine transform for image compression systems

This paper presents a new, unique two-dimensional 8 × 8-point DCT architecture design which employs direct 2-D DCT approach with regular butterfly structure. The architecture employs eight 1-D DCT processors and four post-addition stages to calculate two-dimensional DCT coefficients. Each 1-D DCT processor is designed using Algebraic Integer Encoding architecture which requires no multiplier, therefore the entire proposed 2-D DCT design is multiplierless. Critical path is further shortened by employing five pipeline stages on each compression and decompression system. The proposed image compression system design has a latency of 5 clock cycles. A synthesis result targeting 0.18 μm CMOS technology has proven that the system is able to work in up to 210.684 MHz frequency. Throughput of the compression system can reach 42.02 million macroblocks per second, given that each macroblock consists of 8 × 8 pixels. The proposed design can be claimed to have reached satisfying throughput-area trade-off, given that it yields 6.8 times higher throughput to compensate for the 2.1 times larger area, compared to conventional row-column decomposition based 2-D DCT with 32 multipliers in the 1-D DCT. The aforementioned trade-off is better than several two-dimensional DCT designs that have been published.