Title :
Gate matrix layout based on hierarchical net-list representations
Author :
Yamada, Shoichiro ; Yamazaki, Kazuhiro
Author_Institution :
Dept. of Electr. Eng., Osaka Prefecture Univ., Japan
Abstract :
The authors propose a hierarchical gate matrix layout algorithm based on a new net-list. It has remarkable features such that logical equivalence is considered, and the drawback of the greedy method can be overcome by using special features of multiterminal nets. Experimental results for CMOS circuits are far superior to those obtained by another published method
Keywords :
CMOS integrated circuits; circuit layout CAD; graph theory; logic CAD; logic arrays; minimisation of switching nets; CAD; CMOS circuits; gate arrays; gate matrix layout algorithm; hierarchical net-list representations; logical equivalence; multiterminal nets; Data structures; Educational institutions; Equations; Heuristic algorithms; Logic circuits; Logic functions; MOSFETs; Partitioning algorithms; Wires;
Conference_Titel :
VLSI, 1991. Proceedings., First Great Lakes Symposium on
Conference_Location :
Kalamazoo, MI
Print_ISBN :
0-8186-2170-2
DOI :
10.1109/GLSV.1991.143981
