Title :
GALSY, an automatic layout generator of symbolic layouts from MOS circuit schematics
Author :
Baha, Nadia ; Beddiaf, Meftah ; Gadiri, Abdel-Karim
Author_Institution :
Microelectron. Lab. CDTA, El-Madania, Algeria
Abstract :
The authors deal with a specific aspect of silicon compilation: the translation of an electrical description of an IC design into an IC layout. GALSY, the computer program developed, uses a layout methodology which can be applied to any circuit with sized transistors and any kind of logic (pass-transistor, complementary, precharge, etc.). GALSY makes an intelligent partitioning of a circuit into leaf cells and generates their corresponding layouts. The sublayouts are then automatically placed and ready to be routed
Keywords :
CMOS integrated circuits; MOS integrated circuits; circuit layout CAD; integrated circuit technology; logic CAD; CAD; GALSY; IC design; IC layout; MOS circuit schematics; automatic layout generator; computer program; intelligent partitioning; leaf cells; silicon compilation; sized transistors; symbolic layouts; Design methodology; Integrated circuit layout; Laboratories; Linear matrix inequalities; Logic circuits; MOS devices; MOSFETs; Microelectronics; Optimization methods; Silicon;
Conference_Titel :
VLSI, 1991. Proceedings., First Great Lakes Symposium on
Conference_Location :
Kalamazoo, MI
Print_ISBN :
0-8186-2170-2
DOI :
10.1109/GLSV.1991.143982