Title :
A fast hardware tracker for the ATLAS trigger system
Author_Institution :
Dept. of Phys., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
fDate :
Oct. 24 2009-Nov. 1 2009
Abstract :
As the LHC luminosity is ramped up to the design level of 1034 cm-2s-1 and beyond, the high rates, multiplicities, and energies of particles seen by the detectors will pose a unique challenge. Only a tiny fraction of the produced collisions can be stored on tape and immense real-time data reduction is needed. An effective trigger system must maintain high trigger efficiencies for the physics we are most interested in, and at the same time suppress the enormous QCD backgrounds. This requires massive computing power to minimize the online execution time of complex algorithms. A multi-level trigger is an effective solution for an otherwise impossible problem. The Fast Tracker (FTK) is a proposed upgrade to the ATLAS trigger system that will operate at full Level-1 output rates and provide high quality tracks reconstructed over the entire detector by the start of processing in Level-2. FTK solves the combinatorial challenge inherent to tracking by exploiting the massive parallelism of Associative Memory (AM) that can compare inner detector hits to millions of pre-calculated patterns simultaneously. The tracking problem within matched patterns is further simplified by using pre-computed linearized fitting constants and leveraging fast DSP´s in modern commercial FPGA´s. Overall, FTK is able to compute the helix parameters for all tracks in an event and apply quality cuts in approximately one millisecond. By employing a pipelined architecture, FTK is able to continuously operate at Level-1 rates without deadtime. The system design is defined and studied using ATLAS full simulation. Reconstruction quality is evaluated for single muon events with zero pileup, as well as WH events at the LHC design luminosity. FTK results are compared with the tracking capability of an offline algorithm.
Keywords :
field programmable gate arrays; muon detection; nuclear electronics; particle track visualisation; trigger circuits; ATLAS trigger system; FPGA; Fast Tracker; LHC design luminosity; QCD background suppression; associative memory; digital signal processing; fast hardware tracker; matched patterns; real-time data reduction; reconstruction quality; single muon events; Associative memory; Computer architecture; Detectors; Digital signal processing; Field programmable gate arrays; Hardware; Large Hadron Collider; Parallel processing; Pattern matching; Physics;
Conference_Titel :
Nuclear Science Symposium Conference Record (NSS/MIC), 2009 IEEE
Conference_Location :
Orlando, FL
Print_ISBN :
978-1-4244-3961-4
Electronic_ISBN :
1095-7863
DOI :
10.1109/NSSMIC.2009.5402177