Title :
Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits
Author :
Basu, A. ; Wilson, T.C. ; Banerji, D.K. ; Majithia, J.C.
Author_Institution :
Dept. of Comput. & Inf. Sci., Guelph Univ., Ont., Canada
Abstract :
The authors address the issue of area-time trade off in VLSI circuits using the BILBO methodology of BIST. The issue has been dealt with in an integrated manner. Two distinct approaches, integer linear programming and graph theoretic have been presented
Keywords :
VLSI; built-in self test; digital integrated circuits; graph theory; integer programming; integrated circuit testing; linear programming; BILBO methodology; BIST; VLSI circuits; area-time tradeoff; built-in-self-test; integer linear programming; Built-in self-test; Circuit testing; Cost function; Information science; Integer linear programming; Pattern analysis; Registers; Scheduling algorithm; Test pattern generators; Very large scale integration;
Conference_Titel :
VLSI, 1991. Proceedings., First Great Lakes Symposium on
Conference_Location :
Kalamazoo, MI
Print_ISBN :
0-8186-2170-2
DOI :
10.1109/GLSV.1991.143994
