Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits

Author

Basu, A. ; Wilson, T.C. ; Banerji, D.K. ; Majithia, J.C.

Author_Institution

Dept. of Comput. & Inf. Sci., Guelph Univ., Ont., Canada

fYear

1991

fDate

1-2 Mar 1991

Firstpage

340

Lastpage

341

Abstract

The authors address the issue of area-time trade off in VLSI circuits using the BILBO methodology of BIST. The issue has been dealt with in an integrated manner. Two distinct approaches, integer linear programming and graph theoretic have been presented

Keywords

VLSI; built-in self test; digital integrated circuits; graph theory; integer programming; integrated circuit testing; linear programming; BILBO methodology; BIST; VLSI circuits; area-time tradeoff; built-in-self-test; integer linear programming; Built-in self-test; Circuit testing; Cost function; Information science; Integer linear programming; Pattern analysis; Registers; Scheduling algorithm; Test pattern generators; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1991. Proceedings., First Great Lakes Symposium on

Conference_Location

Kalamazoo, MI

Print_ISBN

0-8186-2170-2

Type

conf

DOI

10.1109/GLSV.1991.143994

Filename

143994

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3335926