The ATLAS RPC ROD for super LHC

The number of interactions per bunch crossing for the upgrade of the Large Hadron Collider is expected to be ten times greater than the actual one. As a consequence, the ATLAS detector for SLHC foresees the use of a larger number of readout channels and also a new trigger level is under development. In order to face with such issue, we developed a new architecture for the Read Out Driver (ROD) for the ATLAS RPC Muon Spectrometer in the barrel region. Presently, each ROD board receives ATLAS RPC Muon readout data and arranges all the data fragments of a sector of the spectrometer in a unique event, sending it to the next acquisition systems. Our new design is based on the new generation Xilinx Virtex5 FPGA and it works with a clock frequency six times greater than the actual bunch crossing rate of the LHC. We also implemented the output channel of the ROD, presently based on S-Link protocol, by using the GTP transceivers inside the FPGA. We present an overview of our design, focusing on the newly added hardware features.