Development of SEU Monitor System for SEU detection and correction in virtex-5 FPGA

Author

Savani, Vijay ; Gajjar, Nagendra

fYear

2011

fDate

8-10 Dec. 2011

Firstpage

1

Lastpage

6

Abstract

In the present era of space application, use of FPGA has been increase dramatically and because of that the developed SEU Monitor System can be used to inject the error manually into the FPGA and after that detection and correction can be confirmed. Also, injected error can be used to verify the effectiveness of the mitigation technique added into the design. We describe the operation and architecture of the proposed logic design as well as its implementation in Xilinx virtex-5 FPGA.

Keywords

field programmable gate arrays; logic design; radiation hardening (electronics); SEU correction; SEU detection; SEU monitor system; Xilinx virtex-5 FPGA; field programmable gate arrays; logic design; mitigation technique; single event upset correction; single event upset detection; single event upset monitor system; Educational institutions; Error correction codes; Field programmable gate arrays; Monitoring; Program processors; Random access memory; Single event upset; Controller Macro; Internal Configuration Access Port (ICAP); SEU Mitigation; Single Event Upset (SEU);

fLanguage

English

Publisher

ieee

Conference_Titel

Engineering (NUiCONE), 2011 Nirma University International Conference on

Conference_Location

Ahmedabad, Gujarat

Print_ISBN

978-1-4577-2169-4

Type

conf

DOI

10.1109/NUiConE.2011.6153268

Filename

6153268