Design analysis of XOR (4T) based low voltage CMOS full adder circuit

This paper presents a comparative study of highspeed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR (4T) design full adder circuits combined in a single unit. This technique helps in reducing the power consumption and the propagation delay while maintaining low complexity of logic design. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid adder circuits in terms of power, delay and power delay product (PDP) at low voltage. Noise analysis shows designed full adder circuit´s work at high frequency and high temperature satisfactorily. Simulation results reveal that the designed circuits exhibit lower PDP, more power efficiency and faster when compared to the available full adder circuits at low voltage. The design is implemented on UMC 0.18μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.