• DocumentCode
    3336619
  • Title

    Can the advantages of RISC be utilized in real time systems?

  • Author

    Steininger, A. ; Schweinzer, H.

  • Author_Institution
    Insts. fur Elektrische Messtech., Tech. Univ. of Vienna, Austria
  • fYear
    1991
  • fDate
    12-14 Jun 1991
  • Firstpage
    30
  • Lastpage
    35
  • Abstract
    Within the last few years a lot of improvements have been made for processor architectures. Average and peak performance are increasing continuously. RISC, caching, pipelining and similar features have become indispensable to many systems. In critical real time systems, however, peak and average values are of minor interest. Because strict deadlines have to be met, only those values may be considered, that can be guaranteed even under adverse conditions. Features like reduced instruction set, caching, pipelining etc. are based upon statistical considerations and do not necessarily improve worst case performance. The question arises, whether new powerful processor architectures-especially the RISC architecture-are suitable for real time systems and if so, under which conditions. Some of the most important hardware features are analyzed to find an answer to this question
  • Keywords
    computer architecture; real-time systems; reduced instruction set computing; Harvard architecture; RISC architecture; hardware features; real time systems; strict deadlines; worst case performance; Application software; Computer architecture; Contracts; Delay; Hardware; Modems; Pipeline processing; Real time systems; Reduced instruction set computing; Registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Real Time Systems, 1991. Proceedings., Euromicro '91 Workshop on
  • Conference_Location
    Paris-Orsay
  • Print_ISBN
    0-8186-2210-5
  • Type

    conf

  • DOI
    10.1109/EMWRT.1991.144076
  • Filename
    144076