A network switch using optical interconnection for high performance parallel computing using PCs: High-density implementation of high-speed signals for a one-chip electronic switch with optical interconnections

A large throughput, low latency network switch (RHiNET-2/SW) has been developed for a distributed parallel computing system. This switch has a new architecture to support low latency “zero-copy” communication in multi-tasking environments. Eight pairs of 800-Mbit/s×12-channel optical interconnection modules and a CMOS ASIC switch are implemented on a compact circuit board. To achieve large-throughput (64 Gbit/s) and low-latency network performance, the SW-LSI has a customized high-speed LVDS I/O interface, and high-speed internal SRAM memory in a 784-pin-BGA one-chip package. Also, we have developed the device implementation technologies to overcome the electrical problems (crosstalk, skew, reflection and noise). These implementation technologies are applicable for switches used in other high-speed networks such as GSN, 4 Gbit/s Fiber Channel or 10 Gbit/s Ethernet